#9 today
YutongChenVictor/NPU-E2E
Verilog Tool
#axidma
#deep-learning
#fpga
#npu
End-to-End NPU: RTL systolic array → AXI4 SoC → TVM compiler → FPGA inference
Created Jul 29, 2026
- Stars
- 13
- Today
- +13
- Forks
- 1
- Quality
- 100/100
- Momentum
- 21
First trending
Jul 29, 2026
first spotted on the list
Best rank
#9
highest position reached
Appearances
2
times on the trending list
Quality score
100
out of 100
Momentum
21
trend strength indicator
Star velocity
0.28
stars per day since creation
Activity — last 60 days
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- Forks
- Merged PRs
- Issues
- Closed issues
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